The volume, use, and complexity of computers and electronic devices are continually increasing. Computers consistently become more powerful and new and improved electronic devices are continually being developed (e.g., digital audio players, video players). Additionally, the growth and use of digital media (e.g., digital audio, video, images, and the like) have further pushed development of these devices. Such growth and development has vastly increased the amount of information desired/required to be stored and maintained for computer and electronic devices.
The use of portable computer and electronic devices has greatly increased demand for memory devices. Digital cameras, digital audio players, personal digital assistants, and the like generally seek to employ large capacity memory devices (e.g., flash memory, smart media, compact flash, . . . ). The increased demand for information storage is commensurate with memory devices having an ever-increasing storage capacity (e.g., increase storage per die or chip). A postage-stamp-sized piece of silicon may, for example, contain tens of millions of transistors, each transistor as small as a few hundred nanometers. The memory cells are typically arranged in an array.
A memory cell can be placed at each intersecting row and column in the array. Typically, a particular memory cell can be accessed by activating its row and then reading or writing the state of its column. Memory sizes are defined by the row and column architecture. For example, a 1024 row by 1024 column memory array can define a memory device having one megabit of memory cells, for example. The array rows can be referred to as wordlines and the array columns can be referred to as bitlines.
In memory cells, one or more bits of data can be stored in and read from respective memory cells. The memory cells can be programmed by various techniques, such as channel hot electron injection (CHEI), and can be erased by various techniques, such as Fowler-Nordheim tunneling. The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the memory cell. For instance, in an erase or write operation the voltages are applied so as to cause a charge to be removed or stored in a charge storage layer of the memory cell.
The trend in semiconductor memory devices is toward higher circuit density with higher numbers of bit cells per device, lower operating voltages, and higher access speeds. To achieve these higher densities there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub-micron levels). However, as the desired scaling down of device dimensions occur, leakage current effects can be increasingly problematic. For example, the channel lengths associated with memory cells can become increasingly shorter as memory devices are scaled down. However, with shorter channel lengths, the employ of CHEI during programming can result in increased undesirable leakage currents associated with the bitlines in the memory array, which can negatively affect programming and overall performance of the memory device. It is desirable to improve the performance of memory devices, including programming of memory devices, by reducing leakage currents associated with programming.